AArch64 - Wikipedia Jump to content Main menu Main menu move to sidebar hide Navigation Main page Contents Current events Random article About Wikipedia Contact us Contribute Help Learn to edit Community portal Recent changes Upload file Special pages Search Search Appearance Donate Create account Log in Personal tools Donate Create account Log in Contents move to sidebar hide (Top) 1 AArch64 Execution state Toggle AArch64 Execution state subsection 1.1 Naming conventions 1.2 AArch64 features 1.2.1 A64 instruction formats 2 ARM-A (application architecture) Toggle ARM-A (application architecture) subsection 2.1 ARMv8.1-A 2.2 ARMv8.2-A 2.2.1 Scalable Vector Extension (SVE) 2.3 ARMv8.3-A 2.4 ARMv8.4-A 2.5 ARMv8.5-A and ARMv9.0-A 2.6 ARMv8.6-A and ARMv9.1-A 2.7 ARMv8.7-A and ARMv9.2-A 2.8 ARMv8.8-A and ARMv9.3-A 2.9 ARMv8.9-A and ARMv9.4-A 2.10 ARMv9.5-A 2.11 ARMv9.6-A 2.12 ARMv9.7-A 3 ARM-R (real-time architecture) 4 References 5 External links Toggle the table of contents AArch64 14 languages Català Deutsch Español Français Magyar Bahasa Indonesia Italiano 日本語 한국어 മലയാളം Português Русский Türkçe Українська Edit links Article Talk English Read Edit View history Tools Tools move to sidebar hide Actions Read Edit View history General What links here Related changes Upload file Permanent link Page information Cite this page Get shortened URL Switch to legacy parser Print/export Download as PDF Printable version In other projects Wikimedia Commons Wikidata item Appearance move to sidebar hide From Wikipedia, the free encyclopedia 64-bit extension of the ARM architecture "},"endianness":{"wt":"[[Endianness#Bi-endianness|Bi]] for data only (little as default, instructions are little)"},"extensions":{"wt":"{{Unbulleted indent list|[[ARMv8-A SVE|SVE]], SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME|Mandatory: [[ARM_architecture_family#Thumb-2|Thumb-2]], [[ARM_architecture_family#Advanced_SIMD_(Neon)|Neon]], VFPv4-D16, VFPv4|Obsolete: [[Jazelle]]}}"},"gpr":{"wt":"31 × 64-bit integer registers<ref name=\"v8arch\"/>"},"fpr":{"wt":"32 × [[128-bit computing|128-bit]] registers<ref name=\"v8arch\"/> for scalar 32- and 64-bit [[IEEE 754|FP]] or [[single instruction, multiple data|SIMD]] FP or integer; or cryptography"}},"i":0}}]}'>ARM AArch64 (64-bit) Introduced 2011; 15 years ago (2011) Version ARMv8-A, ARMv8-R, ARMv9-A Encoding AArch64/A64 and AArch32/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions[1] Endianness Bi for data only (little as default, instructions are little) Extensions SVE, SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME Mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4 Obsolete: Jazelle Registers General-purpose 31 × 64-bit integer registers[1] Floating-point 32 × 128-bit registers[1] for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography AArch64, also known as ARM64, is a 64-bit version of the ARM architecture family, a widely used set of computer processor designs. It was introduced in 2011 with the ARMv8 architecture and later became part of the ARMv9 series. AArch64 allows processors to handle more memory and perform faster calculations than earlier 32-bit versions. It is designed to work alongside the older 32-bit mode, known as AArch32, allowing compatibility with a wide range of software. Devices that use AArch64 include smartphones, tablets, personal computers, and servers. The AArch64 architecture has continued to evolve through updates that improve performance, security, and support for advanced computing tasks.[2] AArch64 Execution state [edit] In ARMv8-A, ARMv8-R, and ARMv9-A, an "Execution state" defines key characteristics of the processor’s environment. This includes the number of bits used in the primary processor registers, the supported instruction sets, and other aspects of the processor's execution environment. These versions of the ARM architecture support two Execution states: the 64-bit AArch64 state and the 32-bit AArch32 state.[3] Naming conventions [edit] 64-bit: Execution state: AArch64 Instruction sets: A64 32-bit: Execution state: AArch32 Instruction sets: A32 + T32 Example: ARMv8-R, Cortex-A32[4] AArch64 features [edit] New instruction set, A64: Has 31 general-purpose 64-bit registers Has dedicated zero or stack pointer (SP) register (depending on instruction) The program counter (PC) is no longer directly accessible as a register Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped) Has paired loads/stores (in place of LDM/STM) No predication for most instructions (except branches) Most instructions can take 32-bit or 64-bit arguments Addresses assumed to be 64-bit Advanced SIMD (Neon) enhanced: Has 32 × 128-bit registers (up from 16), also accessible via VFPv4 Supports double-precision floating-point format Fully IEEE 754 compliant AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers A new exception system: Fewer banked registers and modes Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit Extension: Data gathering hint (ARMv8.0-DGH). AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A, and in all versions of ARMv9-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M. A64 instruction formats [edit] The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28. A64 instruction formats Type Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 op0 0 0 0 0 op1 Scalable Matrix Extensions</span>"}]],"parts":[{"template":{"target":{"wt":"abbr","href":"./Template:Abbr"},"params":{"1":{"wt":"SME"},"2":{"wt":"Scalable Matrix Extensions"}},"i":0}}]}'>SME 1 op0 0 0 0 0 Varies Unallocated 0 0 0 1 Scalable Vector Extensions</span>"}]],"parts":[{"template":{"target":{"wt":"abbr","href":"./Template:Abbr"},"params":{"1":{"wt":"SVE"},"2":{"wt":"Scalable Vector Extensions"}},"i":0}}]}'>SVE 0 0 1 0 Varies Unallocated 0 0 1 1 Data Processing — Immediate PC-rel. op immlo 1 0 0 0 0 immhi Rd Data Processing — Immediate Others sf 1 0 0 01–11 Rd Branches + System Instructions op0 1 0 1 op1 op2 Load and Store Instructions op0 1 op1 0 op2 op3 op4 Data Processing — Register sf op0 op1 1 0 1 op2 op3 Data Processing — Floating Point and SIMD op0 1 1 1 op1 op2 op3 ARM-A (application architecture) [edit] See also: Comparison of ARMv8-A processors Armv8-A platform with Cortex-A57/A53 MPCore big.LITTLE CPU chip Announced in October 2011,[5] ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit Execution state, named "AArch64", and the associated new "A64" instruction set, in addition to a 32-bit Execution state, "AArch32", supporting the 32-bit "A32" (original 32-bit ARM) and "T32" (Thumb/Thumb-2) instruction sets. The latter instruction sets provide user-space compatibility with the existing 32-bit ARMv7-A architecture. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.[1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[6] Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A.[7] The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it only runs in AArch32 mode.[8] ARMv8-A includes VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.[9] An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.[10] For example, the ARM Cortex-A32 supports only AArch32,[11] the ARM Cortex-A34 supports only AArch64,[12] and the ARM Cortex-A72 supports both AArch64 and AArch32.[13] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.[10] ARMv8.1-A [edit] In December 2014, ARMv8.1-A,[14] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation. Instruction set enhancements included the following: A set of AArch64 atomic read-write instructions. Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations: Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half. Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half. The instructions are added in vector and scalar forms. A set of AArch64 load and store instructions that can provide a memory access order that is limited to configurable address regions. The optional CRC instructions in v8.0 become a requirement in ARMv8.1. Enhancements for the exception model and memory translation system included the following: A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled. An increased VMID range for virtualization; supports a larger number of virtual machines. Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism. The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.[15] A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS. Top byte ignore for memory tagging.[16] ARMv8.2-A [edit] ARMv8.2-A was announced in January 2016.[17] Its enhancements fall into four categories: Optional half-precision floating-point data processing (half-precision was already supported, but not for processing, just as a storage format.) Memory model enhancements. Introduction of Reliability, Availability and Serviceability Extension (RAS Extension). Introduction of statistical profiling. Scalable Vector Extension (SVE) [edit] The Scalable Vector Extension (SVE) is licensed as "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads.[18][19] The specification allows for ARM licensees to choose a hard-coded architectural register width between 128 and 2048 bits in multiples of 128. The extension is complementary to and does not replace the NEON extensions. A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor; this computer[20] was the fastest supercomputer in the world for two years, from June 2020[21] to May 2022.[22] A more flexible version, 2x256 SVE, was implemented by the AWS Graviton3 ARM processor. SVE is supported by GCC, with GCC 8 supporting automatic vectorization[19] and GCC 10 supporting C intrinsics. As of July 2020[update], LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.[23] ARMv8.3-A [edit] In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:[24] Pointer authentication (PAC)[25][26] (AArch64 only); mandatory extension (based on a new block cipher, QARMA[27]) to the architecture (compilers need to exploit the security featur…